Metal-oxide-semiconductor (MOS) transistors are common in many types of circuits. N-channel MOS (NMOS) transistors include n-type source and drain regions on either side of a p-type channel, and a gate above and separated from the channel by a dielectric. Applying a certain voltage to the gate can invert the channel to form an n-type conduction region between the drain and source. P-channel MOS (PMOS) transistors include p-type source and drain regions on either side of an n-type channel, and a gate above and separated from the channel by a dielectric. Applying a certain voltage to the gate can invert the channel to form a p-type conduction region between the drain and source. Note that the term metal-oxide-semiconductor transistor, and its use herein, does not limit MOS transistors to having a metal gate. Instead, MOS transistors (including NMOS and PMOS transistors), can include any type of transistor that is known in the art to be referred to by this term, including transistors having polysilicon gates.
Because NMOS and PMOS transistors have different types of drain, source and channel regions, they are typically formed utilizing separate, isolating well regions. For example, if both NMOS and PMOS transistors are to be formed on a p-type substrate (p-substrate), the drains and sources of the NMOS transistors can be formed as n-type regions (n-regions) in the p-substrate, with a portion of the p-type substrate used as the channel. In such circuit structure, an n-type well (n-well) can be formed on top of the p-substrate as a basis for PMOS transistors, the drains and sources of the PMOS transistors formed as p-type regions (p-regions) in the n-well and a portion of the n-well used as the channel. Such n-wells can accommodate either a single PMOS transistor or a plurality of PMOS transistors. One problem with this circuit structure, however, is that all NMOS transistors of a particular circuit may be contained in the same p-substrate. One potential disadvantage of such commonly located NMOS transistors is that they may be subject to a relatively high degree of electrical coupling through the common p-substrate. Such coupling may undesirably increase noise and other unintended deleterious effects.
At least partially for this reason, deep n-wells can be used to isolate NMOS transistors in a similar manner to isolation provided to PMOS transistors by p-wells. A deep n-well can be formed above the p-substrate, a p-well can then be formed above the deep n-well, and such a p-well can be used as a basis for NMOS transistors. That is, drains and sources of NMOS transistors can be formed as n-type regions in the p-well above the deep n-well, with a portion of the p-well used as the channel. As with the n-wells used to form PMOS transistors, the deep n-wells can accommodate either a single NMOS transistor or a plurality of NMOS transistors.
One problem with the use of deep n-wells as a basis for the formation of NMOS transistors, however, is that parasitic capacitances are formed at the border between the p-well and deep n-well, as well as at the border between the deep n-well and the p-well. These parasitic capacitances can be non-linear, varying in value during circuit operation depending on parameters such as the magnitude of a signal propagating through a circuit containing such a circuit structure. Such non-linear parasitic capacitances can have a deleterious effect on circuit performance.